1. Technical Field
The present invention is related generally to an improved data processing system, and in particular to a method and system for improving cache performance in a data processing system. Still more particularly, the present invention is related to a method and apparatus for improved use of a cache shared between two processors in a data processing system.
2. Description of the Related Art
Most early data processing systems consisted basically of a central processing unit, a main memory, and some sort of secondary input/output ("I/O") capability. In these earlier systems, the main memory was the limiting element. Typically, the main memory was designed first and the CPU was then created to match the speed of the memory. This matching was performed to optimize the processing speed and is necessary even with today's high speed computers. Over time, logic circuit speeds increased along with the capacity requirements of main memory. With the need for increasing capacity in the main memory, the speed of the main memory could not keep up with the increasing speed of the CPU. Consequently, a gap developed between the main memory and the processor cycle time, which resulted in un-optimized processing speeds. As a result, a cache memory was developed to bridge the gap between the memory and the processor cycle time.
Using a cache to bridge the performance gap between a processor and main memory has become important in data processing systems of various designs from personal computers to work stations to data processing systems with high performance processors. A cache memory is an auxiliary memory that provides a buffering capability through which a relatively slow main memory can interface with a processor at the processor's cycle time to optimize the performance of the data processing system. Requests are first sent to the cache to determine whether the data or instructions requested are present in the cache memory. A "hit" occurs when the desired information is found in the cache. A "miss" occurs when a request or access to the cache does not produce the desired information. In response to a miss, one of the cache "lines" is replaced with a new one. The method to select a line to replace is called a replacement policy.
A number of different schemes for organizing a cache memory exist. For example, a fully associative mapping organization may be employed whereby a data address may exist in any location in the cache, or a direct mapping scheme may be employed in a cache memory whereby a data address may exist in only one location in the cache. A set associative scheme may be employed by partitioning the cache into distinct classes of lines, wherein each class contains a small fixed number of lines. This approach is somewhere between a direct mapped and a full associative cache. The classes of lines are usually referred to as "congruence classes." The lines in a congruence class are usually referred to as sets (which indicates the number of locations an address can reside) in a congruence class in a set associative cache. More information on cache memories may be found in Stone, High-Performance Computer Architecture, Addison-Wesley Publishing Company, 1987.
Connecting a number of processors to a common cache memory hierarchy may result in poor performance when the processors accesses to a cache behave differently and the replacement policy employed on the cache cause performance degradation to some processors. The same problems may occur when different types of processors having different access schemes are connected to a common cache memory hierarchy. Therefore, it would be advantageous to have an improved method and apparatus for providing balanced cache performance in a cache memory system that contains two or more processors sharing a common memory hierarchy.